1. Field
Exemplary embodiments of the present invention relate to a memory device and a memory system.
2. Description of the Related Art
A memory device includes a plurality of memory cells. Each memory cell of the memory device includes a transistor serving as a switch and a capacitor storing a charge, which represents data. Data is distinguished between a logic high level (logic value ‘1’) and a logic low level (logic value ‘0’) depending on whether there is a charge in the memory cell capacitor, in other words, whether the terminal voltage of the capacitor is high or low.
Data is stored in the form of a charge accumulated in the capacitor, and there is supposed to be no loss of stored data or charge, theoretically. However, because of current leakage in the PN junction of the MOS transistor, the initial charge accumulated in the capacitor may be lost, and consequently the data stored in the memory cell may be lost. To prevent data loss, the data stored in the memory cell is read and the charge is periodically recharged based on the read data before it is lost, which is called a refresh operation. The refresh operation allows the memory device to operate without data loss.
The refresh operation is performed whenever a refresh command is inputted from a memory controller to a memory. The memory controller inputs the refresh command to the memory at predetermined times in consideration of the memory cell's data retention time. Data retention time is defined as how long memory cell data charges may be retained without a refresh operation. Since memory cells included in a memory device are designed to have data retention time that is over a predetermined reference time, refresh operation intervals may be determined in consideration of the reference time.
However, when some memory cells have data retention times that are less than the reference time, due various internal or external factors, the data of the memory cells may not be refreshed fast enough and may be lost. Internal factors may include memory cell defects, such as reduced capacity in memory cell capacitors or high current leakage in memory cell transistors. External factors range from coupling effects on adjacent word lines to over-activated word lines.
FIG. 1 is a circuit diagram illustrating a portion of a cell array included in a memory device. In FIG. 1, BL represents a bit line.
Referring to FIG. 1, three word lines WLK−1, WLK, and WLK+1 are arranged in parallel in the cell array. The word line WLK, with notation “ATACK_ACT”, that has been activated a high number of times (with high activation frequency) or activated for a long time. The word lines WLK−1 and WLK+1 are disposed adjacent to the word line WLK. Also, memory cells CELL_K−1, CELL_K, and CELL_K+1 are coupled with the word lines WLK−1, WLK, and WLK+1, respectively. The memory cells CELL_K−1, CELL_K and CELL_K+1 include cell transistors TR_K−1, TR_K, and TR_K+1 and cell capacitors CAP_K−1, CAP_K, and CAP_K+1, respectively.
When the word line WLK is activated frequently or for a long duration, the voltage of the word line WLK frequently toggles or is maintained at a high level for a long duration, thereby affecting the data stored in the memory cells CELL_K−1 and CELL_K+1, coupled with the word lines WLK−1 and WLK+1, due to coupling effects between the word line WLK and the word lines WLK−1 and WLK+1. Consequently, retention time of the data stored in the memory cells may be reduced.